For tutorial purposes, we will work with a simulated processor

ISC

not RISC (Reduced Instruction Set Computer)

not CISC (Complex Instruction Set Computer)

but ISC (Incredibly Simple Computer)

ISCAL ASC Assembly Language

ISC Instruction Set Design

ISC Internal Structure

(gif file)

Two types of instructions

Another dichotomy

Non-memory access instructions

"Immediate" instructions

loading or adding signal constants

load immediate

Reg[Ra] = C;

add immediate

Reg[Ra] += C;'

A constant can represent an address as well as an arithmetic constant.

Memory Access Intructions

All instructions accessing memory are "register indirect":

The memory address is in a register.

The address is never in the instruction itself

The register must be loaded by another instruction.

Memory Access Instructions

load Ra Rb

reg[Ra] = mem[reg[Rb]];

store Ra Rb

mem[reg[Ra]] = reg[Rb];

Jump Instructions 0111 11000

jeq Ra Rb Rc

Jump to address in Ra

if reg[Rb] == reg[Rc]

sim.

   jne   jlt
   jgt   jlte
   jgte

junc Ra unconditional

ISC:

The control sequencer is a FSM:

Inputs are bits from instruction being interpreted

Outputs are strobes to various registers, 3-state devices, etc

Overall Execution Control

Example

Sub-Control for add instruction